Enhancing drive current and increasing device yield in n-type carbon nanotube field effect transistors

ABSTRACT

Embodiments of the invention are directed to methods and resulting structures for enhancing drive current and increasing device yield in n-type carbon nanotube field effect transistors (CNT FETs) with scaled contacts using a wetting layer. In some embodiments of the invention, a nanotube is formed over a surface of a substrate. An insulating layer is formed over the nanotube such that end portions of the nanotube are exposed. A low work function metal is formed over the end portions of the nanotube and a wetting layer is formed between the low work function metal and the nanotube.

This application is a continuation of U.S. application Ser. No.15/602,890, titled “ENHANCING DRIVE CURRENT AND INCREASING DEVICE YIELDIN N-TYPE CARBON NANOTUBE FIELD EFFECT TRANSISTORS” filed May 23, 2017,the entire contents of which are incorporated herein by reference.

BACKGROUND

The present invention generally relates to fabrication methods andresulting structures for semiconductor devices. More specifically, thepresent invention relates to enhancing drive current and increasingdevice yield in n-type carbon nanotube field effect transistors (CNTFETs) with scaled contacts using a wetting layer.

In contemporary semiconductor device fabrication processes a largenumber of semiconductor devices, such as field effect transistors(FETs), are fabricated on a single wafer. In some FET deviceconfigurations, carbon nanotubes (CNTs) are incorporated in the FETdesign. CNTs provide an intrinsically ultra-thin body and exceptionalelectrical properties (e.g., high drive currents, superior currenton/off ratios, and a long mean-free-path for ballistic transport), whichmakes CNT FETs one of the most promising candidates for the sub-10 nmtechnology node. CNT FETs, like traditional FETs, include a gate, asource, and a drain. In a CNT FET, carbon nanotubes span lengthwisebetween source and drain regions such that the ends of each nanotube arein contact with the source or drain. Each of the carbon nanotubesdefines a conductive media or “channel” for the CNT FET. Gating of thechannel occurs by modulation of the barrier heights of the junctionsbetween the carbon nanotubes and the conductive source/drain regions.

SUMMARY

Embodiments of the present invention are directed to a method forfabricating a semiconductor device. A non-limiting example of the methodincludes forming a nanotube over a surface of a substrate. An insulatinglayer is formed over the nanotube such that end portions of the nanotubeare exposed. A low work function metal is formed over the end portionsof the nanotube. A wetting layer is formed between the low work functionmetal and the nanotube.

Embodiments of the invention are directed to semiconductor device. Anon-limiting example of the semiconductor device includes a nanotubeformed over a surface of a substrate. An insulating layer is patternedon portions of the nanotube such that end portions of the nanotube arenot covered by the insulating layer. A low work function metal is formedover the end portions of the nanotube. A wetting layer is formed betweenthe low work function metal and the nanotube.

Embodiments of the present invention are directed to a method forfabricating a semiconductor device. A non-limiting example of the methodincludes forming a carbon nanotube over a surface of a substrate. Adielectric layer is formed between the carbon nanotube and thesubstrate. An insulating layer is formed over the carbon nanotube.Portions of the insulating layer are removed to expose end portions ofthe carbon nanotube and a low work function metal is formed over theexposed end portions. A wetting layer is formed between the low workfunction metal and the carbon nanotube. A capping layer is formed overthe low work function metal.

Embodiments of the invention are directed to semiconductor device. Anon-limiting example of the semiconductor device includes a dielectriclayer formed on a surface of a substrate. A carbon nanotube is formed ona surface of the dielectric layer. An insulating layer is patterned onportions of the carbon nanotube such that end portions of the nanotubeare not covered by the insulating layer. A low work function metal isformed over the end portions of the nanotube. A wetting layer is formedbetween the low work function metal and the nanotube. A capping layer isformed on the low work function metal.

Embodiments of the invention are directed to an electrode stack of acarbon nanotube field effect transistor. A non-limiting example of theelectrode stack includes a wetting layer formed on an end portion of acarbon nanotube. A low work function metal is formed over the endportion of the carbon nanotube on the wetting layer. A capping layer isformed on the low work function metal.

Additional technical features and benefits are realized through thetechniques of the present invention. Embodiments and aspects of theinvention are described in detail herein and are considered a part ofthe claimed subject matter. For a better understanding, refer to thedetailed description and to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The specifics of the exclusive rights described herein are particularlypointed out and distinctly claimed in the claims at the conclusion ofthe specification. The foregoing and other features and advantages ofthe embodiments of the invention are apparent from the followingdetailed description taken in conjunction with the accompanying drawingsin which:

FIG. 1 depicts a cross-sectional view of a semiconductor structure aftera processing operation according to one or more embodiments of thepresent invention;

FIG. 2 depicts a cross-sectional view of the semiconductor structureafter a processing operation according to one or more embodiments of thepresent invention;

FIG. 3 depicts a cross-sectional view of the semiconductor structureafter a processing operation according to one or more embodiments of thepresent invention;

FIG. 4 depicts a cross-sectional view of the semiconductor structureafter a processing operation according to one or more embodiments of thepresent invention;

FIG. 5 depicts a cross-sectional view of the semiconductor structureafter a processing operation according to one or more embodiments of thepresent invention;

FIG. 6 depicts a flow diagram illustrating a method according to one ormore embodiments of the invention; and

FIG. 7 depicts the effect of a wetting layer formed according to one ormore embodiments of the invention on drive currents and device yieldsfor n-type carbon nanotubes.

The diagrams depicted herein are illustrative. There can be manyvariations to the diagram or the operations described therein withoutdeparting from the spirit of the invention. For instance, the actionscan be performed in a differing order or actions can be added, deletedor modified.

In the accompanying figures and following detailed description of theembodiments of the invention, the various elements illustrated in thefigures are provided with two or three digit reference numbers. Withminor exceptions, the leftmost digit(s) of each reference numbercorrespond to the figure in which its element is first illustrated.

DETAILED DESCRIPTION

For the sake of brevity, conventional techniques related tosemiconductor device and integrated circuit (IC) fabrication may or maynot be described in detail herein. Moreover, the various tasks andprocess steps described herein can be incorporated into a morecomprehensive procedure or process having additional steps orfunctionality not described in detail herein. In particular, varioussteps in the manufacture of semiconductor devices andsemiconductor-based ICs are well known and so, in the interest ofbrevity, many conventional steps will only be mentioned briefly hereinor will be omitted entirely without providing the well-known processdetails.

Turning now to an overview of technologies that are more specificallyrelevant to aspects of the present invention, as previously notedherein, CNT FETs are positioned as one of the most promising candidatesfor the sub-10 nm technology node. There are challenges, however, inintegrating CNT FETs into the complementary metal oxide semiconductor(CMOS) architecture. For example, the implementation of a carbonnanotube-based CMOS device with low standby power dissipation requiresthe formation of n-type and p-type CNT FETs having comparably robusthigh-performance, which is difficult to achieve using conventionalmethods.

The type of CNT FET (n or p-type) is determined by the nature of thecontact formed between the contact metal and the carbon nanotube. Ingeneral, the use of a high work function contact metal results in p-typebehavior, while the use of a low work function contact metal results inn-type behavior. Consequently, the relative performance of n-type CNTFETs, in terms of drive current, is worse than their p-typecounterparts. Conventional approaches to improving the drive current ofn-type CNT FETs have not been wholly successful. Some conventionalsolutions employ work function engineering at the contact in conjunctionwith potential engineering of the device channel by dielectricpassivation to produce comparable n-type versus p-type behavior. Thesetypes of approaches, however, limit device scaling by increasing thecomplexity of fabrication and reducing device yield. Solutions forincreasing the n-type CNT FET drive current should be scalable, i.e.,the device yield should not significantly degrade as the contact length(Lc) is decreased.

Turning now to an overview of aspects of the present invention, one ormore embodiments of the invention provide methods and structuresconfigured to increase both the drive current in n-type carbon nanotubesand the yield of operational devices in which the contact lengths (Lc)are scaled. In some embodiments of the invention, this can beaccomplished by using a wetting layer between the nanotube and the lowwork function contact metal. For example, titanium, a metal that isknown to wet a carbon nanotube surface well, can be used as the wettinglayer. In some embodiments of the invention, the wetting layer isdeposited onto the carbon nanotube surface prior to the main contactmaterial of the electrode (e.g., a CNT n-type metal material such asSc). The wetting layer improves physical and electrical contact to thecarbon nanotube and provides a more efficient injection of chargecarriers through the carbon nanotube/electrode interface. In thismanner, incorporation of the wetting layer results in both a largerdrive current and an improved device yield.

Turning now to a more detailed description of aspects of the presentinvention, FIG. 1 depicts a cross-sectional view of a structure 100having a carbon nanotube 102 formed over a substrate 104 during anintermediate operation of a method of fabricating a semiconductor deviceaccording to one or more embodiments of the invention. The carbonnanotube 102 can be deposited, transferred, or grown using knownfront-end-of-line (FEOL) nanotube fabrication techniques. For example,in some embodiments of the invention the carbon nanotube 102 is placedon the substrate 104 using a spin on coating process. The thickness ofthis coating is preferably substantially less than the length of thecarbon nanotubes such that when the coating is spun onto the substrate,the carbon nanotubes will tend to lay flat, i.e., with their axessubstantially parallel to the plane of the substrate 104. In otherembodiments of the invention, the carbon nanotube 102 is formed usingCVD, plasma enhanced CVD (PECVD), chemical solution deposition,electrophoretic deposition, or other like processes. The carbon nanotube102 can have a diameter ranging from 0.1 nm to 10 nm. The carbonnanotube 102 can have a contact length (i.e., the length of an end ofthe carbon nanotube in contact with an electrode) ranging from 5 nm toover a micron. For example, the contact length of the carbon nanotube102 can be 40 nm or 750 nm, although other lengths are within thecontemplated scope of the invention.

The substrate 104 can include any suitable substrate material, such as,for example, semiconductor or conducting material. Semiconductormaterials include monocrystalline Si, SiGe, SiC, III-V compoundsemiconductor, II-VI compound semiconductor, orsemiconductor-on-insulator (SOI). Conducting materials include metal(e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt,copper, aluminum, lead, platinum, tin, silver, gold), conductingmetallic compound material (e.g., tantalum nitride, titanium nitride,tantalum carbide, titanium carbide, titanium aluminum carbide, tungstensilicide, tungsten nitride, ruthenium oxide, cobalt silicide, nickelsilicide), conductive carbon, graphene, or any suitable combination ofthese materials. The substrate 104 can further include dopants that areincorporated during or after deposition. For example, the substrate 104can be doped during deposition (in-situ doped) or doped following theepitaxy by adding n-type dopants (e.g., As, P, Sb) or p-type dopants(e.g., Ga, B, BF₂, Al). The dopant concentration can range from 1×10¹⁹cm⁻³ to 2×10²¹ cm⁻³, or between 1×10²⁰ cm⁻³ and 1×10²¹ cm⁻³.

A dielectric layer 106 (also known as a gate dielectric) can be formedbetween the carbon nanotube 102 and the substrate 104. The dielectriclayer 106 can be any suitable dielectric material, such as, for example,silicon dioxide, silicon nitride, and high-k dielectric material. Thehigh-k dielectric material can be a dielectric material having adielectric constant greater than, for example, 3.9, 7.0, or 10.0.Non-limiting examples of suitable materials for the high-k dielectricmaterial include oxides, nitrides, oxynitrides, silicates (e.g., metalsilicates), aluminates, titanates, nitrides, or any combination thereof.Examples of high-k dielectric materials with a dielectric constantgreater than 7.0 include, but are not limited to, metal oxides such ashafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride,lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconiumsilicon oxide, zirconium silicon oxynitride, tantalum oxide, titaniumoxide, barium strontium titanium oxide, barium titanium oxide, strontiumtitanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalumoxide, and lead zinc niobate. The high-k dielectric materials canfurther include dopants such as, for example, lanthanum and aluminum.The dielectric layer 106 can be formed by any suitable depositionprocesses, for example, CVD, PECVD, ALD, evaporation, PVD, chemicalsolution deposition, or other like processes.

FIG. 2 depicts a cross-sectional view of the structure 100 after formingan insulating layer 200 over the carbon nanotube 102 and the dielectriclayer 106 during an intermediate operation of a method of fabricating asemiconductor device according to one or more embodiments of theinvention. The insulating layer 200 can include a dielectric material,such as, for example, SiN, SiC, SiOC, SiCN, BN, SiBN, SiBCN, SiOCN,SiO_(x)N_(y), and combinations thereof. The dielectric material can be alow-k material having a dielectric constant less than about 7, less thanabout 5, or even less than about 2.5. The insulating layer 200 can beformed using known deposition processes, such as, for example, CVD,PECVD, ALD, PVD, chemical solution deposition, or other like processes.

The insulating layer 200 is patterned to expose end portions of thecarbon nanotube 102. In some embodiments of the present invention,portions of the insulating layer 200 are removed to formed source/draintrenches 202. The source/drain trenches 202 define the source/draincontact regions. The patterned insulating layer 200 prevents oxidationof the low work function metal 400 (contact metal) at the nanotube/metalinterface (as depicted in FIG. 4). The insulating layer 200 can bepatterned using, for example, a wet etch, a dry etch, or a combinationthereof. In some embodiments of the present invention, the insulatinglayer 200 is patterned with hydrogen silsesquioxane (HSQ), which can bespun onto a surface of the insulating layer 200 and patterned byelectron-beam lithography. The pattern can then be transferred into theinsulating layer 200.

FIG. 3 depicts a cross-sectional view of the structure 100 after forminga wetting layer 300 on the exposed end portions of the carbon nanotube102 and on portions of the dielectric layer 106 during an intermediateoperation of a method of fabricating a semiconductor device according toone or more embodiments of the invention. A material of the wettinglayer 300 is selected such that the wetting layer 300 makes goodphysical and electrical contact with a surface of the carbon nanotube102. For example, the wetting layer 300 can include any suitable metalor metallic material known to wet a carbon nanotube surface. In someembodiments of the present invention, the wetting layer 300 includestitanium, nickel, or palladium.

The wetting layer 300 can be deposited by any suitable depositionprocess, such as, for example, CVD, PECVD, PVD, plating, thermal ore-beam evaporation, sputtering, or combinations thereof. The wettinglayer 300 can be formed to any desirable thickness. In some embodimentsof the present invention, the wetting layer 300 partially fills thesource/drain trenches 202. In some embodiments of the present invention,the wetting layer 300 is formed to a thickness of about 0.1 nm to about2 nm. In some embodiments of the present invention, the wetting layer300 is co-formed with the low work function metal 400 (as depicted inFIG. 4) and the capping layer 500 (as depicted in FIG. 5). Co-formingthe wetting layer 300 in this manner advantageously increases the finaldevice drive current relative to the maximum drive current achievable byforming the wetting layer 300 separately using a different depositionsystem.

FIG. 4 depicts a cross-sectional view of the structure 100 after forminga low work function metal 400 over the exposed end portions of thecarbon nanotube 102 and on portions of the dielectric layer 106 duringan intermediate operation of a method of fabricating a semiconductordevice according to one or more embodiments of the invention. Asdiscussed previously herein, the low work function metal 400 facilitatesn-type behavior in CNT FETs. The low work function metal 400 can be madeof any suitable material for n-type CNT FETs, such as, for example,scandium, calcium, potassium, sodium, erbium.

The low work function metal 400 (also known as a contact electrode) ispatterned using, for example, known electron-beam or photolithographytechniques. For example, in some embodiments of the present invention,the low work function metal 400 is formed using a polymethylmethacrylate (PMMA) resist in conjunction with electron-beamlithography. In some embodiments of the present invention, the low workfunction metal 400 is formed on the wetting layer 300 to fill theremaining portions of the source/drain trenches 202. In some embodimentsof the present invention, the low work function metal 400 is formed to athickness of about 1 nm to about 50 nm, although other thicknesses arewithin the contemplated scope of the invention. In some embodiments ofthe present invention, the low work function metal 400 is overfilledinto the source/drain trenches 202, forming overburdens above a surfaceof the insulating layer 200.

FIG. 5 depicts a cross-sectional view of the structure 100 after forminga capping layer 500 over the low work function metal 400 during anintermediate operation of a method of fabricating a semiconductor deviceaccording to one or more embodiments of the invention. The capping layer500 can include any inert metal that can be deposited onto the low workfunction metal 400 and serves to prevent deleterious reactions (e.g.,oxidation) of the low work function metal 400 with the environment(i.e., water and oxygen). For example, the capping layer 500 can includegold, palladium, titanium, or aluminum. The capping layer 500 can beformed to a same thickness or a different thickness as the low workfunction metal 400. In some embodiments of the present invention, thecapping layer 500 is formed to a thickness of about 1 nm to about 50 nm,although other thicknesses are within the contemplated scope of theinvention. As illustrated in FIG. 5, the completed CNT FET includes alow work function metal 400 (contact electrodes) serving as the sourceand drain and a conducting substrate 104 serving as the gate.

FIG. 6 depicts a flow diagram 600 illustrating a method for forming asemiconductor device according to one or more embodiments of theinvention. As shown at block 602, a nanotube is formed over a surface ofa substrate. The nanotube can be formed in a similar manner as thecarbon nanotube 102 depicted in FIG. 1 according to one or moreembodiments.

As shown at block 604, an insulating layer is formed over the nanotube.The insulating layer can be formed in a similar manner as the insulatinglayer 200 depicted in FIG. 2. As shown at block 606, end portions of thenanotube are exposed. As discussed previously herein, the insulatinglayer can be patterned to expose the end portions of the nanotube.

As shown at block 608, a low work function metal is formed over the endportions of the nanotube. The low work function metal can be formed in asimilar manner as the low work function metal 400 depicted in FIG. 4. Asdiscussed previously herein, the low work function metal can include anysuitable material for n-type CNT FETs, such as, for example, scandium,and can have a thickness of about 1 nm to about 50 nm.

As shown at block 610, a wetting layer is formed between the low workfunction metal and the nanotube. The wetting layer can be formed in asimilar manner as the wetting layer 300 depicted in FIG. 3. As discussedpreviously herein, a material of the wetting layer is selected such thatthe wetting layer makes good physical and electrical contact with asurface of the nanotube. In some embodiments of the present invention,the wetting layer includes titanium having a thickness of about 0.1 nmto about 1 nm.

FIG. 7 depicts the effect of a wetting layer formed according to one ormore embodiments of the invention on drive currents and device yieldsfor n-type carbon nanotubes. All devices were formed with scandium/goldelectrode stacks and the channel length was controlled to about 40 nm.As illustrated in FIG. 7, the wetting layer improved the average drivecurrent from about 0.46 μA to about 0.77 μA. The wetting layer alsoimprove device yield with 81 out of 367 devices working without thewetting layer and 226 out of 367 devices working with the wetting layer.

Various embodiments of the present invention are described herein withreference to the related drawings. Alternative embodiments can bedevised without departing from the scope of this invention. Althoughvarious connections and positional relationships (e.g., over, below,adjacent, etc.) are set forth between elements in the followingdescription and in the drawings, persons skilled in the art willrecognize that many of the positional relationships described herein areorientation-independent when the described functionality is maintainedeven though the orientation is changed. These connections and/orpositional relationships, unless specified otherwise, can be direct orindirect, and the present invention is not intended to be limiting inthis respect. Similarly, the term “coupled” and variations thereofdescribes having a communications path between two elements and does notimply a direct connection between the elements with no interveningelements/connections between them. All of these variations areconsidered a part of the specification. Accordingly, a coupling ofentities can refer to either a direct or an indirect coupling, and apositional relationship between entities can be a direct or indirectpositional relationship. As an example of an indirect positionalrelationship, references in the present description to forming layer “A”over layer “B” include situations in which one or more intermediatelayers (e.g., layer “C”) is between layer “A” and layer “B” as long asthe relevant characteristics and functionalities of layer “A” and layer“B” are not substantially changed by the intermediate layer(s).

The following definitions and abbreviations are to be used for theinterpretation of the claims and the specification. As used herein, theterms “comprises,” “comprising,” “includes,” “including,” “has,”“having,” “contains” or “containing,” or any other variation thereof,are intended to cover a non-exclusive inclusion. For example, acomposition, a mixture, process, method, article, or apparatus thatcomprises a list of elements is not necessarily limited to only thoseelements but can include other elements not expressly listed or inherentto such composition, mixture, process, method, article, or apparatus.

Additionally, the term “exemplary” is used herein to mean “serving as anexample, instance or illustration.” Any embodiment or design describedherein as “exemplary” is not necessarily to be construed as preferred oradvantageous over other embodiments or designs. The terms “at least one”and “one or more” are understood to include any integer number greaterthan or equal to one, i.e. one, two, three, four, etc. The terms “aplurality” are understood to include any integer number greater than orequal to two, i.e. two, three, four, five, etc. The term “connection”can include an indirect “connection” and a direct “connection.”

References in the specification to “one embodiment,” “an embodiment,”“an example embodiment,” etc., indicate that the embodiment describedcan include a particular feature, structure, or characteristic, butevery embodiment may or may not include the particular feature,structure, or characteristic. Moreover, such phrases are not necessarilyreferring to the same embodiment. Further, when a particular feature,structure, or characteristic is described in connection with anembodiment, it is submitted that it is within the knowledge of oneskilled in the art to affect such feature, structure, or characteristicin connection with other embodiments whether or not explicitlydescribed.

For purposes of the description hereinafter, the terms “upper,” “lower,”“right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” andderivatives thereof shall relate to the described structures andmethods, as oriented in the drawing figures. The terms “overlying,”“atop,” “on top,” “positioned on” or “positioned atop” mean that a firstelement, such as a first structure, is present on a second element, suchas a second structure, wherein intervening elements such as an interfacestructure can be present between the first element and the secondelement. The term “direct contact” means that a first element, such as afirst structure, and a second element, such as a second structure, areconnected without any intermediary conducting, insulating orsemiconductor layers at the interface of the two elements.

The terms “about,” “substantially,” “approximately,” and variationsthereof, are intended to include the degree of error associated withmeasurement of the particular quantity based upon the equipmentavailable at the time of filing the application. For example, “about”can include a range of ±8% or 5%, or 2% of a given value.

The phrase “selective to,” such as, for example, “a first elementselective to a second element,” means that the first element can beetched and the second element can act as an etch stop.

The term “conformal” (e.g., a conformal layer) means that the thicknessof the layer is substantially the same on all surfaces, or that thethickness variation is less than 15% of the nominal thickness of thelayer.

The terms “epitaxial growth and/or deposition” and “epitaxially formedand/or grown” mean the growth of a semiconductor material (crystallinematerial) on a deposition surface of another semiconductor material(crystalline material), in which the semiconductor material being grown(crystalline overlayer) has substantially the same crystallinecharacteristics as the semiconductor material of the deposition surface(seed material). In an epitaxial deposition process, the chemicalreactants provided by the source gases can be controlled and the systemparameters can be set so that the depositing atoms arrive at thedeposition surface of the semiconductor substrate with sufficient energyto move about on the surface such that the depositing atoms orientthemselves to the crystal arrangement of the atoms of the depositionsurface. An epitaxially grown semiconductor material can havesubstantially the same crystalline characteristics as the depositionsurface on which the epitaxially grown material is formed. For example,an epitaxially grown semiconductor material deposited on a {100}orientated crystalline surface can take on a {100} orientation. In someembodiments of the invention, epitaxial growth and/or depositionprocesses can be selective to forming on semiconductor surface, and cannot deposit material on exposed surfaces, such as silicon dioxide orsilicon nitride surfaces.

As previously noted herein, for the sake of brevity, conventionaltechniques related to semiconductor device and integrated circuit (IC)fabrication may or may not be described in detail herein. By way ofbackground, however, a more general description of the semiconductordevice fabrication processes that can be utilized in implementing one ormore embodiments of the present invention will now be provided. Althoughspecific fabrication operations used in implementing one or moreembodiments of the present invention can be individually known, thedescribed combination of operations and/or resulting structures of thepresent invention are unique. Thus, the unique combination of theoperations described in connection with the fabrication of asemiconductor device according to the present invention utilize avariety of individually known physical and chemical processes performedon a semiconductor (e.g., silicon) substrate, some of which aredescribed in the immediately following paragraphs.

In general, the various processes used to form a micro-chip that will bepackaged into an IC fall into four general categories, namely, filmdeposition, removal/etching, semiconductor doping andpatterning/lithography. Deposition is any process that grows, coats, orotherwise transfers a material onto the wafer. Available technologiesinclude physical vapor deposition (PVD), chemical vapor deposition(CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE)and more recently, atomic layer deposition (ALD) among others.Removal/etching is any process that removes material from the wafer.Examples include etch processes (either wet or dry), chemical-mechanicalplanarization (CMP), and the like. Reactive ion etching (RIE), forexample, is a type of dry etching that uses chemically reactive plasmato remove a material, such as a masked pattern of semiconductormaterial, by exposing the material to a bombardment of ions thatdislodge portions of the material from the exposed surface. The plasmais typically generated under low pressure (vacuum) by an electromagneticfield. Semiconductor doping is the modification of electrical propertiesby doping, for example, transistor sources and drains, generally bydiffusion and/or by ion implantation. These doping processes arefollowed by furnace annealing or by rapid thermal annealing (RTA).Annealing serves to activate the implanted dopants. Films of bothconductors (e.g., poly-silicon, aluminum, copper, etc.) and insulators(e.g., various forms of silicon dioxide, silicon nitride, etc.) are usedto connect and isolate transistors and their components. Selectivedoping of various regions of the semiconductor substrate allows theconductivity of the substrate to be changed with the application ofvoltage. By creating structures of these various components, millions oftransistors can be built and wired together to form the complexcircuitry of a modern microelectronic device. Semiconductor lithographyis the formation of three-dimensional relief images or patterns on thesemiconductor substrate for subsequent transfer of the pattern to thesubstrate. In semiconductor lithography, the patterns are formed by alight sensitive polymer called a photo-resist. To build the complexstructures that make up a transistor and the many wires that connect themillions of transistors of a circuit, lithography and etch patterntransfer steps are repeated multiple times. Each pattern being printedon the wafer is aligned to the previously formed patterns and slowly theconductors, insulators and selectively doped regions are built up toform the final device.

The flowchart and block diagrams in the Figures illustrate possibleimplementations of fabrication and/or operation methods according tovarious embodiments of the present invention. Variousfunctions/operations of the method are represented in the flow diagramby blocks. In some alternative implementations, the functions noted inthe blocks can occur out of the order noted in the Figures. For example,two blocks shown in succession can, in fact, be executed substantiallyconcurrently, or the blocks can sometimes be executed in the reverseorder, depending upon the functionality involved.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments described. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiments, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdescribed herein.

1. A method for forming a semiconductor device, the method comprising:forming a nanotube over a surface of a substrate; forming an insulatinglayer over the nanotube; exposing end portions of the nanotube; forminga low work function metal over the end portions of the nanotube; forminga wetting layer between the low work function metal and the nanotube andforming a capping layer over the low work function metal, wherein thecapping layer comprises gold.
 2. The method of claim 1 furthercomprising forming a dielectric layer between the nanotube and thesubstrate.
 3. (canceled)
 4. The method of claim 1, wherein the nanotubecomprises a carbon nanotube.
 5. The method of claim 1, wherein thesubstrate comprises doped silicon or a metal.
 6. The method of claim 1,wherein the insulating layer comprises silicon nitride.
 7. The method ofclaim 1, wherein the low work function metal comprises scandium.
 8. Themethod of claim 7, wherein the low work function metal further comprisesa thickness of about 10 nm to about 50 nm.
 9. The method of claim 1,wherein the wetting layer comprises titanium.
 10. The method of claim 9,wherein the wetting layer further comprises a thickness of about 0.1 nmto about 1 nm.
 11. The method of claim 2, wherein the dielectric layercomprises silicon dioxide.
 12. (canceled)
 13. The method of claim 1,wherein the capping layer further comprises a thickness of about 10 nmto about 50 nm.
 14. The method of claim 1, wherein the wetting layercomprises titanium, the low work function metal comprises scandium, andthe capping layer comprises gold.
 15. A method for forming a carbonnanotube field effect transistor, the method comprising: forming acarbon nanotube over a surface of a substrate; forming a dielectriclayer between the carbon nanotube and the substrate; forming aninsulating layer over the carbon nanotube; removing portions of theinsulating layer to expose end portions of the carbon nanotube; forminga low work function metal over the end portions of the carbon nanotube;and forming a wetting layer between the low work function metal and thecarbon nanotube; and forming a capping layer over the low work functionmetal.
 16. The method of claim 15, wherein the wetting layer comprisestitanium, the low work function metal comprises scandium, and thecapping layer comprises gold.